Sr ASIC Engineer


• Design, simulate, and layout small families of standard cells for use in ROIC array design.

• Optimize clock and signal paths and buffer sizes.

• Design, simulate, implement and test digital circuits and systems using VHDL/Verilog based RTL design flow (FPGAs/ASICs) and transistor level circuit design.

• Document and specify digital functions and systems.

• Design and program digital systems using microcontrollers and hybrid FPGA/CPU approach.

• Support transition to manufacturing.

• Develop test procedures.

Job Requirements        • BS/MS/PHD Electrical Engineering, Computer Engineering, or Physics.

• Min. 5 years of experience years experience in comparable field.

• Must have a strong digital design background with practical understanding of designs all the way down to transistor level

• Must be fluent in RTL design using VHDL/Verilog.

• Solid understand of digital timing and static timing analysis.

• Proficient in system level simulation for large digital systems using high-­level test benches and hardware-­in-­loop automated testing

• Demonstrated success with team-­oriented environment.

• Good communication skills.

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